Review Article | Open Access
Genquan Han, Yue Peng, Huan Liu, Jiuren Zhou, Zhengdong Luo, Bing Chen, Ran Cheng, Chengji Jin, Wenwu Xiao, Fenning Liu, Jiayi Zhao, Shulong Wang, Xiao Yu, Yan Liu, Yue Hao, "Ferroelectric Devices for Intelligent Computing", Intelligent Computing, vol. 2022, Article ID 9859508, 18 pages, 2022. https://doi.org/10.34133/2022/9859508
Ferroelectric Devices for Intelligent Computing
Recently, transistor scaling is approaching its physical limit, hindering the further development of the computing capability. In the post-Moore era, emerging logic and storage devices have been the fundamental hardware for expanding the capability of intelligent computing. In this article, the recent progress of ferroelectric devices for intelligent computing is reviewed. The material properties and electrical characteristics of ferroelectric devices are elucidated, followed by a discussion of novel ferroelectric materials and devices that can be used for intelligent computing. Ferroelectric capacitors, transistors, and tunneling junction devices used for low-power logic, high-performance memory, and neuromorphic applications are comprehensively reviewed and compared. In addition, to provide useful guidance for developing high-performance ferroelectric-based intelligent computing systems, the key challenges for realizing ultrascaled ferroelectric devices for high-efficiency computing are discussed.
In the past few decades, the advancements in information technology have improved the global economy while changing people’s lifestyle. This revolution relies on two aspects, the establishment of information-processing theories and development of electronic hardware. These established theories and the software based on them enable computers to process highly complicated tasks. Simultaneously, with the rapid evolution of computing hardware, the computing capability (CC) of devices has considerably expanded as it is mainly driven by transistor scaling. However, in the past decade, transistor scaling is approaching its physical limit, hindering the further development of the CC. In addition, as shown in Figure 1(a), computing systems need to overcome several challenges for processing increasing amounts of data in the present era. The issue of “heat wall” , which hinders the enhancement of the main frequency of the processer owing to the rising power density and heating effect, needs to be addressed. Furthermore, the issue of “memory wall” , which is caused by large performance or area gap between the logic device and memory cell, and the von Neumann bottleneck , which refers to the delay and power issues caused by the inefficient data transfer between the memory module and logic processor, need to be overcome. As the demand for computing power increases, new materials and novel transistors should be explored to support the development of CC-based emerging technologies.
Intelligent computing is a new research area whose development highly relies on the improvement of CC [4, 5]. However, owing to the aforementioned computing bottlenecks, new storage and logic devices with higher speed and lower power consumption, such as memristors and phase-change memory devices, need to be introduced [6–9].
Among all the available technological alternatives, ferroelectric devices can overcome the “heat wall,” “memory wall,” and von Neumann bottleneck, as shown in Figure 1(b). As identified more than a century ago, the polarization of ferroelectric materials can be retained even after the removal of the external electric field. Ferroelectric materials have been widely used as special-purpose memories in devices such as aerospace storage devices [10, 11]. In traditional ferroelectric materials, such as zirconium titanate (PZT) or barium titanate (BTO), the domain size is critical for retaining the polarization [12, 13]. The thickness scale of these materials is greater than 10 nm; thus, they are not adaptive to the nanoscale IC fabrication process. New ferroelectric materials and devices with high scalability potential can solve these issues. For example, a negative capacitor field-effect transistor (NCFET) with hafnium-based ferroelectric gate oxides can enhance the subthreshold swing (SS) to reduce the driving voltage of the integrated circuits (ICs), thus effectively suppressing the power consumption and heating effect . Ferroelectric capacitor-based random access memory (FeRAM) and ferroelectric field-effect transistor- (FeFET-) based memory show excellent performance in dynamic random access memory (DRAM) replacement and embedded applications [15, 16]. In addition, FeFETs can be used as artificial neurons and synaptic devices in the neuromorphic system to overcome the von Neumann bottleneck [17, 18].
In this article, we focus on emerging ferroelectric devices applicable for highly efficient and intelligent computing. High-κ and other novel ferroelectric materials are reviewed in Section 2. This is followed by a comprehensive summary of the authors’ study on low-power ferroelectric logic devices (Section 3), high-performance memory arrays (Section 4), and neuromorphic computing demonstrations (Section 5). Section 6 concludes this article with future prospects for emerging ferroelectric devices and their application in intelligent computing.
2. Emerging Ferroelectric Materials
Ferroelectricity has been observed in many types of materials. However, when the film thickness is reduced to less than 10 nm, most of the conventional ferroelectric materials lose their polarization characteristics at 25°C , rendering the ferroelectric devices incompatible with the nanoscale very-large-scale-integration-circuit processing technologies. The discovery of the polarization effect in high-κ materials, which are the commonly used gate-oxide materials for nanoscale MOSFETs, is a breakthrough for the mass production of ferroelectric transistors. In this section, we focus on the polycrystalline Hf-based and amorphous oxide-based ferroelectric materials and devices that have been shown to be compatible with the CMOS fabrication process. In addition, some recently reported novel ferroelectric materials and devices are also briefly described.
2.1. Doped-HfO2 Ferroelectric Materials
Since the discovery of ferroelectricity in doped-HfO2 films in 2011 , ferroelectric field-effect transistors (FeFETs) and ferroelectric random access memory (FeRAM) have received significant attention [21–25]. Polycrystalline doped-HfO2 films are considered as promising gate-oxide materials owing to their excellent ferroelectric properties as well as high compatibility with the ultrascale CMOS process. Compared with traditional perovskite ferroelectric materials, doped-HfO2 ferroelectric films exhibit a higher coercive field (Ec~1–2 MV/cm) and lower permittivity (~30), which are desirable for low-power nonvolatile memory devices with excellent retention characteristics.
Doped-HfO2 materials have three types of crystal structures, namely, monoclinic, tetragonal, and cubic structures. The phase transition can be achieved through several approaches, for example, application of mechanical stress, postdeposition annealing, and application of higher deposition pressure [26, 27]. In 2011, Böscke et al. discovered that the use of Si as a dopant could facilitate the formation of asymmetric orthorhombic-phased HfO2 and hence the generation of ferroelectricity in the film . Subsequently, various elements were introduced as dopants for the formation of ferroelectric doped-HfO2 materials, such as HfZrOx (HZO), HfAlOx (HAO), HfLaOx (HLO), and HfGeOx[28, 29]. Among these doped-HfO2 ferroelectric materials, HZO was studied most intensively owing to its remarkable ferroelectric characteristics, particularly at a Zr composition between 0.3 and 0.7. From the perspective of fabrication, it is easier to achieve stable and uniform HZO ferroelectric films by atomic layer deposition and annealing. Moreover, the annealing temperature required for forming the ferroelectric HZO thin films can be as low as 400°C , while that for HfO2 films doped with other elements is usually greater than 650°C [31–34].
Recently, material properties, such as oxygen vacancy, doping concentration, film stress, and surface/interfacial energy, have been reported to influence the ferroelectric properties of doped-HfO2 ferroelectric films. Peng et al.  measured the polarization-voltage (P-V) curves of the HZO films with different Zr compositions. Figure 2 shows the P-V curves for TaN/HZO/TaN samples. For the postannealing temperature within the range of 500–550°C, the P-V curves of the HZO metal-insulator-metal (MIM) structures tend to saturate in a subloop state. As the Zr composition increases, the remnant polarization (Pr) of the film becomes stronger, and the hysteresis loop becomes narrower at a zero voltage bias; these can be considered to be the superimposed antiferroelectric-like characteristics [33, 36]. Pesic et al. [37, 38] reported the use of electrodes with different work functions to introduce a built-in electric field into the antiferroelectric layer to achieve a stable ferroelectric phase. Reyes-Lillo et al.  reported that the conversion of ZrO2 from the antiferroelectric to the ferroelectric state could be realized by introducing compressive strain into the ZrO2 film. In addition, Materlik et al.  suggested that the stability of the metastable ferroelectric phase was related to the surface energy effect and proposed a model based on the surface energy.
2.2. Amorphous Oxide-Based Ferroelectric Materials
Excessive research has focused on promoting the fabrication and application of polycrystalline doped-HfO2 FeFETs [41, 42]. However, when the devices are scaled down to the nanometer level, the domain- and grain-boundary-induced variations in the polycrystalline doped-HfO2 ferroelectric films degrade their performance and reliability [43, 44]. Thus, an amorphous or single crystalline ferroelectric material is desirable for achieving high-performance and reliable ferroelectric devices .
Recently, ferroelectric-like phenomena have been observed in amorphous oxides. These phenomena are related to the mobile oxygen vacancies in the amorphous materials. Because amorphous materials lack domains or boundaries, the amorphous ferroelectric oxides mentioned above can be used for achieving nanoscale transistors exhibiting low device variation and nonvolatile storage function [46, 47]. Amorphous materials that exhibit polarization switching include ZrO2 , Al2O3 [49, 50], HfO2 , La2O3 , and TiO2 , which are compatible with the conventional CMOS process and have been employed as high-κ gate dielectrics for logic transistors.
Liu et al.  reported the P-V loop characteristics of a TaN/α-ZrO2/Ge device, demonstrating a ferroelectric-like device behavior with a nonzero Pr less than 2 μC/cm2. In contrast to doped-HfO2 ferroelectric devices, no wake-up or imprint phenomena were observed for the ferroelectric α-ZrO2 capacitors. Peng et al. [49, 50] reported the integration of amorphous Al2O3 films in MIM and MOS capacitors to achieve polarization-switching characteristics, as shown in Figures 3(a) and 3(b). Piezoresponse force microscopy (PFM) tests of the Al2O3 film on TaN/Si samples were conducted, demonstrating the opposite natures of ferroelectric dipoles on the surface of Al2O3 on TaN. X-ray photoelectron spectrum (XPS) measurement showed that a TaOx interface layer was formed between TaN and Al2O3. This layer provided oxygen vacancies in the form of Al suboxides due to the scavenging effect, as shown in Figures 3(c) and 3(d). Feng et al.  strategically modulated the deposition conditions of Al2O3 in TaN/Al2O3/Si capacitors to change the film property from paraelectric to ferroelectric-like. The oxygen-deficient Al2O3 layer with the migration barrier is the key for achieving ferroelectric-like properties. It can be hypothesized that as more oxygen vacancies (Vo+) are generated in the Al2O3 film, the migration barrier for Vo+ and O2− becomes weaker. The in situ ARXPS results clearly show the scavenging effect at the interface, which occurs upon TaN film deposition, leading to the formation of the TaON interfacial layer. The TaON interfacial layer was proposed to act as an oxygen reservoir. The transport of the Vo+ and O2− pair was introduced to explain the dynamic process of polarization switching, as shown in Figures 3(e) and 3(j), with the consideration of the gate leakage current. With an applied gate bias, the ions pass through the migration barrier of the oxide layer to the interface. The barrier will “lock” these separated charging ions even after the applied voltage is removed. This assists in generating interface-induced long-range polarization.
2.3. Other Emerging Ferroelectric Materials
The development of ferroelectric transistors is a significant breakthrough in a wide range of intelligent computing applications such as nonvolatile memories, logic devices, and synaptic transistors. Such devices generally have planar MOSFET structure, in which the ferroelectric/semiconductor heterostructure is the fundamental building block . Therefore, the realization of high-quality ferroelectric/semiconductor heterostructures is the core of this device integration technology. In traditional direct deposition techniques such as atomic layer deposition (ALD) and pulsed laser deposition (PLD), the integration of ferroelectric oxide thin films on conventional semiconductors is often hindered by critical issues in the growth process, including oxidation of the semiconductor surface, high thermal budget for ferroelectric growth, and lattice mismatch . Atomically thin two-dimensional (2D) semiconductors that can form heterostructures using the van der Waals (vdW) force may be promising candidates to overcome this limitation and broaden the material set for high-quality ferroelectric/semiconductor heterostructures . A typical fabrication process of the ferroelectric/2D semiconductor heterostructure is shown in Figure 4(a). With this transfer-based integration, precrystallized ferroelectric and semiconductor layers can be bonded at low processing temperatures. Such a physical assembly method is based on the vdW interaction between the layers and does not involve a direct chemical process, which is required in the aforementioned direct deposition approaches. Thus, versatile ferroelectric/2D semiconductor heterostructures with a clean interface can be easily realized through vdW integration without any strict requirements for direct chemical vapor deposition, such as lattice matching and high-temperature postfabrication crystallization. Moreover, compared to conventional bulk semiconductors, 2D semiconductors can enhance the modulation of the gate electric field owing to the reduced dielectric screening and therefore suppress the leakage current in the FETs owing to the confined charge carriers; they can also realize novel functions that are not possible using bulk semiconductor devices [58–60]. Therefore, 2D semiconductors provide an untapped material platform for achieving unprecedented advancements in the device performance and functionality of ferroelectric transistors .
In this section, we present a timely review of the recent advancements in intelligent computing applications based on the ferroelectric transistors prepared using 2D semiconductors (Figure 4). Nonvolatile memories are among the first applications of 2D ferroelectric-gate transistors [62, 63]. A typical 2D FeFET structure consisting of a ferroelectric gate (PZT thin film) and an approximately 2 nm thick 2D WSe2 channel is shown in Figure 4(b) . Excellent nonvolatile memory properties including a high switching ratio of 104, robust retention up to 1000 s, and excellent fatigue properties have been obtained in such a 2D FeFET (Figure 4(b)) . Here, during the 2D FeFET fabrication process, 2D semiconductor flakes are mechanically exfoliated onto PZT thin films without any high-temperature annealing. Benefiting from such a vdW integration process, the ferroelectric film/2D semiconductor structure is expected to retain a virginal interface with a genuine vdW gap; thus, it is expected to solve the interface problems observed in conventional semiconductor-based FeFETs and exhibit a smaller depolarization field as well as a superior retention performance . Beyond the binary memory effect induced by full polarization switching in 2D FeFETs, fractional polarization variation subjected to mixed ferroelectric domain configurations can be exploited as an approach to tune the electrical properties of 2D channels. Memristive behaviors featuring multilevel resistance states have been achieved in such devices by carefully modulating the switching history of 2D FeFETs. These devices can be used as 2D memristive ferroelectric transistors and synaptic devices . Recently, light-controlled 2D memristive ferroelectric transistors have been proposed based on the efficient optoelectronic properties of 2D semiconductors. As shown in Figure 4(c), Luo et al. demonstrated the optoelectronic tunability of the memristive effect in WS2/PZT FeFETs, wherein optically controlled long-term potentiation (LTP) and electrically modulated long-term depression (LTD) were achieved . The optically mediated resistance switching behavior is based on light-triggered ferroelectric domain switching (PFM-recorded domain evolution images are shown in Figure 4(c)), which is due to the interplay between the photoinduced charge dissociation process in the 2D channels and the ferroelectric depolarization effect in the PZT thin films. This heterostructure-enabled new functionality suggests that the versatile coupling effects between the ferroelectrics and 2D semiconductors might lead to the development of more intriguing function devices. In addition to memristive-enabled analog computing devices, the ferroelectric-induced nonvolatile memory effect has been further explored for constructing nonvolatile logic devices. For example, dual-ferroelectric-gated 2D transistors, in which the double gate terminals could serve as two logic input variables for the one-transistor- (1T-) structured Boolean logic gate, have been proposed, as shown in Figure 4(d) . Unipolar MoS2 and ambipolar MoTe2 semiconductor channels can be used to operate 2D dual-gate FeFETs as AND and XOR logic gates, respectively. A heterogenous 2T-cell-based nonvolatile half adder was also developed by accurately connecting these two devices. Because dual-ferroelectric-gated transistors cannot be easily achieved using conventional materials and fabrication techniques, the use of 2D materials and vdW integration lead to a new pathway for device structure and function innovations of FeFETs. In addition, 2D NCFETs can be operated with subthermal switching slopes and integrated with silicon-based substrates . By exploiting the intrinsic mechanical flexibility of 2D materials, a full vdW MoS2/CuInP2S6- (CIPS-) based flexible NCFET has been realized . This device can further extend the application spectrum of 2D electronic devices (Figure 4(e)).
In addition to the aforementioned devices based on the homogeneous ferroelectric-gating effect, local ferroelectric-polarization-mediated 2D homojunctions can be used to enhance the CC in intelligent computing applications. Because of the ambipolar electronic properties and ultrathin nature of 2D semiconductors, electrostatic doping has been used as an efficient approach for selectively achieving p- and n-type 2D FETs [72–74]. The high doping capacity and local domain engineering ability of ferroelectrics compared to those of conventional dielectrics render them a promising gate material for nonvolatile and reconfigurable 2D homojunctions . For example, Wu et al. showed that reconfigurable p-n, n-p, p-p, and n-n homojunctions could be realized in a single transistor using the local ferroelectric gating in split-ferroelectric-gated MoTe2 transistors (Figure 4(f)) . Furthermore, using the scanning probe technique with nanometer-level precision, arbitrary and rewritable nanopatterns with distinct electronic properties could be created on-demand in 2D semiconductors atop a ferroelectric gate. This technique was used to locally create p-n homojunctions in 2D MoS2/P(VDF-TrFE) transistors, as shown in Figure 4(g) . With such a device, excellent photodetection characteristics including a responsivity of approximately 12 A/W and detectivity over 1013 Jones in tip writing were achieved. Lipatov et al. further demonstrated the facile generation and erasing of conducting channels in unipolar MoS2 channels atop the PZT ferroelectric film (Figure 4(h)), indicating an innovative nanoscopic engineering methodology for ferroelectric memory devices . In general, beyond conventional ferroelectric-gate devices, 2D semiconductor-based ferroelectric-gated transistors have shown potential for more sophisticated device functions and high CMOS compatibility for device fabrication, paving the way for the development of intelligent computing devices.
3. Ferroelectric-Based Efficient Logic Device: NCFET
Reducing the driving voltage of the chips is a potential method to break the “heat wall,” and its feasibility is highly dependent on the SS of the transistor. Ferroelectric NCFETs, together with the voltage amplification effect, can overcome Boltzmann’s tyranny and achieve an SS of sub-60 mV/dec. Thus, they are regarded to have one of the most promising device architectures for ultralow-power applications and can reenable the rapid development of the IC industry [77–79]. Comprehensive investigations of NCFETs in terms of understanding the mechanisms involved, analysis of characteristics, determining design rules, and improvement in reliability have been performed in both the industry and academia [80–90]. This section focuses on the evolution of the NCFET technology and advancements in this field.
In 2008, Salahuddin and Datta proposed the concept of NCFET . As shown in Figure 5(a), an NCFET is realized by replacing the conventional dielectric in a planar MOSFET with a ferroelectric material. The device utilizes negative differential capacitance () to achieve surface potential amplification and an SS of sub-60 mV/dec. Prior to 2015, there was a lack of systematical characterization of its basic electrical performance, which hindered the practical application of its highly efficient logic device concept. To bridge this gap, Han et al. performed a series of studies on this topic [49, 92–94]. In 2016, Zhou et al. reported the first ferroelectric Ge and GeSn NCFETs (Figures 5(a)–5(c)) . Incorporated with CMOS-compatible ferroelectric HZO, the Ge and GeSn NCFETs demonstrated an SS of less than 60 mV/dec, enhanced on-state current, suppressed off-state current, and improved transconductance. Additionally, the other important characteristics of NCFETs were systematically reported, particularly the unique output and inversion capacitance characteristics, demonstrating the typical phenomenon of negative differential resistance (NDR) and inversion capacitance peaks (Figures 5(d) and 5(e)) . As shown in Figure 5(d), the NDR effect causes a decrease in current with increasing drain voltage, which not only shows the potential for short channel effect (SCE) suppression but also opens a new pathway to improve the intrinsic gain or output resistance for analog applications. Figure 5(e) shows the capacitance characteristics of an NCFET and its reference device. Several times of enhancement in inversion capacitance are gained in NCFET, and the mechanisms of accelerated switching and enhanced gate control were revealed. The voltage gain characteristics of a specially designed NCFET with an exposed internal metal gate were also investigated to monitor the response of the internal gate voltage () with . Figure 5(f) shows the curves of the NCFETs, where the voltage amplification () was achieved for both forward and reverse sweeping of , corresponding to the abrupt switching in curves at the same location of . This confirms that the voltage gain was induced by negative capacitance (NC) effects and the subsequently low SS (sub-60 mV/dec) [96, 97]. Thus far, the electrical characteristics of NCFETs have been systematically characterized and used for various NCFET-based applications.
After a careful investigation of the basic electrical characteristics of NCFETs, a thorough examination of the appropriate design rules for the transistors should be performed to optimize their hysteretic behaviors and frequency characteristics. According to Salahuddin and Datta, the inventors of NCFET, a ferroelectric capacitor () usually demonstrates an intrinsic phenomenon of polarization hysteresis loops, leading to the instability and invalidity of the NC effect as well as the hysteretic behavior of NCFET . Nonetheless, the NCFET can be stabilized using a series-placed conventional dielectric capacitances (). That is, the electrical performance of NCFETs depends on the capacitance matching degree. Hence, several research groups have focused on the elimination of hysteretic characteristics of the NCFETs [14, 81, 96, 98–104]. Since 2017, Zhou et al. systematically investigated the design rules for capacitance matching in NCFETs from various aspects, including the ferroelectric properties , thickness of the ferroelectric films (), and area ratio of to (). As illustrated in Figure 5(g), the increased rapid thermal annealing temperature, decreased , and increased can effectively modulate the magnitude of hysteresis, validating the design rule for capacitance matching and its effectiveness in optimizing the electrical performance of NCFETs. The frequency characteristics are the next key bottleneck for the practical application of NCFETs, owing to the requirement of high-speed switching for ICs. In 2015, Khan investigated the frequency characteristics of a PZT using the R-C delay system. The switching delay of the PZT capacitor was shown to have a decreasing tendency with a decrease in resistance connected in series. It was predicted that the intrinsic delay of the ferroelectric material could be as low as 19.9 ns. However, research on the frequency characteristics of NCFETs is still lacking. In 2017, Xidian University and GlobalFoundries  investigated the frequency characteristics of NCFETs and proposed a high-frequency compatible metal-ferroelectric-insulator-semiconductor (MFIS) architecture to realize an SS of sub-60 mV/dec in NCFETs operated up to the gigahertz scale. The MFIS structure could achieve faster polarization switching owing to its large leakage channel (Figure 5(h)) .
For the validation of the NC concept and the theoretical and experimental evaluations of the design rules, more attention was focused on understanding the NC effect. In 2016, Zubko et al. theoretically predicted the existence of the NC effect as a result of the field-drivable ferroelectric dipoles, which has piqued considerable interest in this field . In 2018, Samsung  reported that the NC effect was caused by the ferroelectric polarization delay and could only be obtained during the transient response. In 2019, Yadav et al.  and Hoffmann et al.  separately demonstrated that the NC effect could be observed at both the micro- and macrolevels. However, the origin of the NC effect and its impact on the characteristics of NCFETs remained unknown. In 2019, Han et al. reported two important studies [107, 108] (Figure 5(i)), which experimentally clarified that the NC effect originated from the depolarization field and that incomplete polarization switching was sufficient to produce the NC effect for hysteresis-free NCFETs to achieve enhanced electrical performance. These studies are of great importance for the optimization of NCFET in terms of basic performance and reliability characteristics.
Owing to the discovery of the CMOS-compatible doped-HfO2 ferroelectric materials, both ferroelectric memory and ferroelectric-based efficient logic devices have gained increasing attention. However, because of the intrinsic properties of doped-HfO2 ferroelectric materials, the related ferroelectric devices always suffer from various reliability issues, such as the threshold voltage shift induced by the imprinting effect, performance variation induced by the wake-up effect, and insufficient endurance characteristics. In 2019, Peng et al. reported a new type of ferroelectric-like materials, known as the nanocrystal-embedded insulator (NEI), consisting of a main dielectric body and an embedded nanocrystal-ZrOx . The mechanism of such materials is quite different from the mainstream mechanism of doped-HfO2 ferroelectric materials. The ferroelectricity of the former is not based on the nonasymmetric ferroelectric domains and can thus circumvent the performance shift appearing in the latter. Figure 5(j) shows the schematic of the NEI NCFETs and HRTEM images of the gate stack. Such novel NCFETs fabricated by nanocrystal ZrO2 grains can also achieve a sub-60 mV/dec SS, an enhanced on-state current, a suppressed off-state current, and the NDR effect. In addition, the utilization of such types of ferroelectric materials can expand the range of gate insulators for use in future electronic devices to achieve improved electrical performance, high device reliability, and good process compatibility.
In this section, we comprehensively reviewed the revolution of NCFETs. Over the past decade, the concept of NCFETs was established theoretically and demonstrated experimentally from various perspectives, such as the basic electrical characteristics, typical phenomena, performance optimization, frequency characteristics, mechanism analysis, and structure innovations. Additional applications based on the excellent electrical properties of NCFETs have been proposed, particularly ultralow power applications, small short-channel effect (SCE) applications, and analog applications. In the future, the understanding of the NC mechanisms at the atomic level, better circuit design, and process compatibility should be focused upon, which can facilitate the practical application of NCFETs in the post-Moore era.
4. Ferroelectric-Based High-Performance Memories
The conventional dynamic RAM (DRAM) uses a capacitor to store data. Cell leakage current and wire parasitic capacitance in the ICs pose significant challenges for further scaling down the cell size. Nevertheless, the ferroelectric capacitor can store information through the charge, which is nonvolatile, and possesses a much higher charge density per area. Therefore, replacing the dielectric material of a flash device with doped-HfO2 ferroelectrics or amorphous oxide ferroelectrics to realize an FeFET is an alternative method to further reduce the power or delay of these memories, which will help bridge the gap between the performances of these devices and logic devices.
Gong et al. recently demonstrated doped-HfO2 one transistor on capacitor (1T-1C) FeRAM for high-speed embedded nonvolatile memory (eNVM) and DRAM replacement applications . This device exhibited a low operation voltage of 2.5 V and a high operation speed of 14 ns. Many relevant studies [111–114] reported that the engineering of material and device structure could improve the performance of the FeRAM. It was observed that the oxygen content or oxygen vacancy affected the o-phase content in the HZO film . Therefore, could be optimized through oxygen content engineering, such as by tuning the oxygen deposition time in the ALD film deposition process, changing the electrode materials, and depositing an additional interfacial layer/seed layer [115–117]. Although the feasibility of doped-HfO2 FeRAM has been proven, some of its key parameters, such as endurance, cannot meet the requirement for practical applications.
To address this issue, Peng et al.  reported an HfO2-ZrO2 superlattice (SL) FE film as the gate dielectric for FeFETs. A compressive strain was introduced into the HfO2 layer owing to the lattice mismatch between HfO2 and ZrO2, which was conducive to form the nonpolar phase of the ferroelectric (FE) film. The deviation of the alternate oxygen rows from the centers of the four nearest Hf/Zr atoms induced a dipole moment and resulted in a ferroelectric behavior. The SL MIM capacitors exhibited significantly improved endurance performance and fatigue recovery capability compared to the HZO MIM capacitors, as shown in Figures 6(a) and 6(b). Xiao et al.  designed and realized a 16-kbit 1T-1C FeRAM array with BEOL-integrated HZO-based ferroelectric capacitors. The ferroelectric characteristics of the test key (1C) and single cell (1T-1C) were discussed. Endurance up to 109 cycles at the array level was achieved for the first time. Figure 6(c) showed the local layout view of the 1T-1C FeRAM test chip with different blocks in terms of the WL driver, sense amplifier, and cell matrix. Cell matrices with a size of , , and were used to investigate the effect of bitline length on the memory window (MW).
Flash memories are also widely used for embedded and storage applications. An FeFET can be considered a floating gate device, in which the gate dielectric is replaced by ferroelectric oxides. This device exhibits the following characteristics: (1) enhanced CMOS process compatibility owing to lower operation voltage and simpler structure, (2) low power owing to the electric-field-driven polarization switching mechanism, (3) low write latency enabled by fast polarization switching, and (4) nondestructive read-out owing to the three-terminal device structure. Thus, an FeFET array-based memory based on flash memory could be realized without redesigning the architecture and circuits. A typical FeFET memory array and its peripheral circuitry are shown in Figure 7(a). The architecture includes a coder/decoder, I/Os, sensitive amplifiers, write buffers, controllers, and a data bus; this architecture is similar to that of a NOR flash. At the circuit level, the only difference is that the write operation for an FeFET can be realized using an electric field; however, for the flash device, this operation is realized by hot carrier injection. Recently, GlobalFoundries has demonstrated FeFET-based memory with 28 nm bulk technology and 22 nm FDSOI CMOS technology [41, 119], indicating the possibility of FeFET-based circuit integration on advanced CMOS platforms.
Typically, the gate stack of FeFETs is in the form of MFIS structures. The threshold voltage () of FeFETs can be modulated by an external voltage pulse applied at the gate electrode using two stable polarization states and polarization switching of ferroelectric materials . Thus, information can be stored as different states in an FeFET. When a sufficiently large positive voltage pulse is applied, the polarization of the ferroelectric oxide is reversed (down state), and the FeFET switches to a low- state. On the contrary, if a sufficiently large negative voltage is applied, the polarization reverses again (up state) and the FeFET switches to a high- state. The voltage difference between the of these two different states is defined as the MW. The MW of FeFETs with a sufficiently large can be approximately evaluated by the following equation : where α is a coefficient that represents the MW degradation caused by nonideal effects such as charge trapping, is the electric field, and is the ferroelectric film thickness.
An amorphous ZrO2-based ferroelectric FET has been demonstrated to improve the performance and compatibility of the FeFET [49, 121]. For embedded NVM applications, a 0.78 V MW can be achieved using a program voltage of 2.7 V and an erase voltage of −2.8 V with a pulse width of 5 μs. For embedded DRAM applications, program and erase speeds of approximately 10 ns can be achieved using a program voltage of 7.4 V and an erase voltage of −8.6 V, with an MW larger than 0.2 V . An amorphous Al2O3 nonvolatile FET can achieve a MW above 0.85 V under ±3 V at a pulse width of 100 ns under the program/erase (P/E) condition (Figure 7(b)) . The P/E voltage can be further reduced to ±1.6 V, thus exhibiting the potential of the device for applications at a lower operation voltage compared to that of doped-HfO2 FeFETs. Amorphous oxide-based FeFETs show good endurance characteristics but a severe degradation in the retention performance. Nonvolatile FETs with α-Al2O3 show a stable MW without any degradation over 106 P/E cycles at ±3 V and 100 ns (Figure 7(c)) . The trapping/detrapping effect is also a key factor that influences the MW of these devices.
5. Ferroelectric Devices for Neuromorphic Computing
Since the inception of the computing system, data storage and processing have been separate functions owing to the large difference between the two in terms of the working speeds, operation modes, and fabrication technology. The von Neumann architecture has addressed these compatibility problems, leading to developments in the field of computing. However, the performance and efficiency of data-centricity are restricted by circuit delay and power issues owing to the large time and power consumption required for the transport and exchange of data between the memory and processing modules, which is referred to as the von Neumann bottleneck. Thus, novel computing devices and architecture have attracted considerable interest to resolve this issue.
One of the possible solutions is neuromorphic computing. The information storage and processing in the brain are hybrid functions in nature. Imitation of the neuron system for information processing is referred to as neuromorphic computing. The most important components in such a system are artificial neurons and synapses. According to reported studies [94, 122–135], FeFETs can implement both artificial neurons and synapses. For applications in neurons, FeFETs functioning as pulsed neural networks have been commonly used in previous studies. Because FeFETs have hysteretic characteristics, they can possess both on and off states and can be used as a switch to charge or discharge a capacitor. In a study by Wang et al. , a unique device model was used in the form of a one-transistor-one-FeFET structure. This model could control the gate voltage of the FeFET to produce an arbitrary output of the neuron and an inhibitory input. Furthermore, Yan et al. conducted a study based on Ref.  to investigate the effect of voltage bias on the output voltage of a neuron ; they explained the mechanism associating the inhibitory input with the computational biological neuron model. In addition, Chen et al. fabricated a novel leaky-FeFET (L-FeFET) to mimic biological neurons . Luo et al.  improved the L-FeFET model and experimentally demonstrated that the hardware cost could be considerably reduced using an architecture comprising one resistor and two transistors. They added an inhibitory port to realize spiking neural networks, providing a promising direction for the integration of neuromorphic computing systems in the future.
Moreover, FeFETs can simultaneously perform storage and processing functions; therefore, they can be used for artificial synapse applications involving spike neural networks (SNNs)  and convolutional neural network (CNNs) . Many studies have investigated the writing methods of FeFETs as synapses in neural networks to achieve better performance. For a single FeFET device, Jerry et al. demonstrated three write pulse schemes: identical pulses, pulses with incremental voltages, and pulses with incremental pulse widths affecting the update of the switch polarization . From the results , it was concluded that the use of write pulses with suitable incremental voltage could help achieve excellent linearity and superior accuracy in neural network simulation. Furthermore, Nguyen et al. implemented a writing method involving fixing the gate pulse while gradually increasing the drain pulse, and compared the differences to impose incremental gate pulses . The effects of different ferroelectric structures  and working temperature  were also examined in the application of deep neural networks. The charge trapping and release dynamics of HZO-based FeFET were explored, and a gate-stack design for enlarging the MW was determined . For FeFET-based memory arrays with NOR and NAND architectures, the write disturbance effect for unselected memory cells was extensively tested . Charge trapping and polarization switching were found to be the two mechanisms that affect the write disturbance. In contrast, Choe et al. proposed a three-dimensional AND-type architecture for matrix-vector multiplication and demonstrated its performance on deep neural networks .
In addition to polycrystalline doped-HfO2 FeFETs, metal/amorphous dielectric/semiconductor gate stacks exhibit the switchable ferroelectric-like P, which can be used to implement analog synapses and SNNs. Recently, an analog synapse device based on a nonvolatile field-effect transistor (NVFET) with the amorphous ZrO2 dielectric has been fabricated and demonstrated. This ZrO2-based device exhibited superior synaptic characteristics, including good symmetry and linearity for both potentiation and depression, with small cycle-to-cycle variations. The ratio of the maximum to minimum conductance () of the device was 130, and the middle states was over 30. The spike-timing-dependent plasticity (STDP) was reproduced in the device. Based on emulated STDP functions, an SNN-based architecture has been constructed, and it has been shown that the offline and online training recognition accuracies reach 94 and 87%, respectively . Moreover, various synaptic behaviors including long-term potentiation (LTP), long-term depression (LTD), and STDP have been reproduced in ferroelectric-like FETs integrated with 3 and 6 nm thick Al2O3 dielectrics when different types of electrical stimuli were applied to the gate, as shown in Figure 8(a) . The dynamic response of the LTP and LTD is illustrated in Figure 8(b) . An SNN architecture based on the properties of analog synapses was also built. Online training was conducted based on the synaptic characteristics of the device, and a decent accuracy (>80%) was achieved for fixed amplitude potentiation/depression pulses (±3 V/100 ns, Figure 8(c)). All of these results indicate that the amorphous Al2O3 synaptic device has high application potential in neuromorphic computing .
Novel amorphous-dielectric-based ferroelectric-like devices can also be used for realizing CNNs owing to their advantages in terms of linearity and asymmetry, which help increase the accuracy of these devices. In Ref. , the NEI layer (3.6 nm thickness) comprised ferroelectric nanocrystals embedded in amorphous Al2O3. Thus, the operating voltages and depolarization effects were lower compared to those of the conventional doped-HfO2 films, which can be used in a CNN architecture. With fixed-amplitude potentiation/depression pulses with a 100 ns pulse width, an NEI FeFET synapse achieved a weight update with small nonlinearity (, ) and asymmetry factors. A CNN was designed and emulated for a Mixed National Institute of Standards and Technology (MNIST) dataset, and it achieved an online training accuracy of 92% . Furthermore, FeFETs with the amorphous Al2O3 gate dielectric exhibit high endurance, decent memory window with low program/erase voltage, and analog synapse properties, achieving a high learning accuracy for the CNNs . As shown in Figure 9(a), multiple cycles of consecutive alternating potentiation/depression pulses were applied to the FeFET, showing highly repeatable conductance profiles, which can be used in the CNN weight update. A CNN architecture utilizing a sign backpropagation (SBP) algorithm was designed based on the one-transistor-one-FeFET synapse cell to investigate the impact of the FeFET synapse performance on the online training, as shown in Figure 9(b). Online neural network training simulations parameterized by the FeFET synapses were conducted, and a high learning accuracy (>94%) was achieved for a fixed pulse amplitude of potentiation/depression pulses (±2 V, 100 ns) with a read gate voltage of −0.1 V, as shown in Figure 9(c). Figure 9(d) shows the statistical plots of the learning accuracy of the neural network operated with different and potentiation/depression conditions of the FeFET synapses. A high learning accuracy (>90%) was achieved owing to the improvement in the synaptic behavior.
In addition, ferroelectric tunnel junctions (FTJs) have attracted significant attention for synaptic device applications owing to their compact device structure, nondestructive readout scheme, and high write/read access speeds . FTJ is a two-terminal resistive nonvolatile memory device consisting of a nanometer-thick ferroelectric film and conductive metal electrodes at both ends. The operation of the FTJ memory device relies on the modulation of the interface barrier height owing to the ferroelectric switching and quantum tunneling through an ultrathin barrier layer. The modulation of the tunneling current due to ferroelectric polarization reversal is called the tunneling electroresistance (TER) effect and is used to store/process information as an artificial synapse.
Thus far, three types of ferroelectric materials have been adopted in the current FTJ technology: ABO-type perovskites [137, 138], such as BaTiO3 (BTO) and PbZr0.2Ti0.8O3; 2D van der Waals materials [139, 140], such as CuInP2S6 (CIPS) and α-In2Se3; and binary oxides, such as HfO2 and Hf0.5Zr0.5O2 (HZO) [141, 142]. The first two types of FTJs can achieve a large TER ratio, but they are incompatible with the modern CMOS process. With the discovery of ferroelectricity in the polycrystalline HfxZr1-xO, doped-HfO2 FTJs have been extensively explored, and a TER ratio up to 100 can be achieved.
The development of FTJs is still in the preliminary stage. The suppression of the sneak current and distribution correlation of the high/low resistance in the array structure still requires further analysis. Fujii et al.  reported that doped-HfO2-based self-compliant FTJs could achieve a low operating current of less than 100 nA, low operating voltage of 2 V, and switching ratio exceeding 10. Recently, Goh et al.  reported a self-rectifying FTJ with a TiN/HZO/TaN/W stack, a low operating current of less than 100 nA, high TER (~102), and 108 endurance cycles.
FTJs are also widely used in nonvolatile memories and neurosynaptic computing, particularly for artificial synaptic applications. FTJs have been demonstrated to be able to mimic various synaptic behaviors under different types of pulses, including STDP, LTP, and LTD. Ryu et al.  reported the continuously tunable conductivity of FTJs with a Ti/Au/Al2O3/HZO/Si structure and identified that the conductance increased with the number of potentiation pulses and decreased with the number of depression pulses; the results revealed that the synaptic weight was continuously tunable. In addition, the STDP function of biologic synapses in FTJs was demonstrated. Ryu et al.  reported the evaluation of synaptic properties, such as the LTD and LTP, of the HZO FTJs using three different pulse schemes. The conductance state gradually changed with the number of pulses, and more than 30 stable intermediate states were achieved. The pattern recognition rate based on the MNIST dataset was calculated using a neural network simulator with a multilayer perceptron, and an accuracy of approximately 90% was achieved. In addition, Xiao et al.  simulated FTJ devices and demonstrated that the best synapse characteristics could be obtained through the pulse amplitude modulation scheme; furthermore, they suggested that increasing the amplitudes between consecutive pulses would further improve the linearity, number of states, and conductance ratio.
6. Future Outlook
Over the past decade, remarkable progress of nanoscale ferroelectric devices based on emerging oxide materials has been achieved, from the conceptual stage to industrial demonstration. In this article, we attempted to categorize the state-of-the-art ferroelectric devices as low-power logic devices, high-performance memory cells, and neuromorphic devices for intelligent computing to meet the requirements of different applications. If the tradeoff between process compatibility and device performance can be achieved, NCFET, FeRAM, or FeFET memory and ferroelectric synapse devices can be integrated into the same chip to realize a multifunctional intelligent computing system. The architecture and computing algorithms for ferroelectric devices need to be further improved. Based on the progress achieved in the ferroelectric device-processing technology, the integration of low-power logic, high-performance memories, and neuromorphic systems on one chip seems to be feasible with continuous process improvement. This will help realize the development of high-performance and high-efficiency intelligent computing systems in the future.
Conflicts of Interest
The authors declare no conflicts of interest.
This work was supported by the Major Scientific Research Project of Zhejiang Lab (Grant No. 2021MD0AC01), the Natural Science Foundation of Zhejiang Province (Grant No. LQ21E070002), the Zhejiang Province Key R&D Programs (Grant Nos. 2022C01232 and 2021C05004), and the National Natural Science Foundation of China (Grant No. 92064001).
- M. A. Zidan, J. P. Strachan, and W. D. Lu, “The future of electronics based on memristive systems,” Nature Electronics, vol. 1, no. 1, pp. 22–29, 2018.
- S. A. McKee, “Reflections on the memory wall,” in Proceedings of the 1st Conference on Computing Frontiers, p. 162, Ischia Italy, April 2004.
- N. K. Upadhyay, H. Jiang, Z. Wang, S. Asapu, Q. Xia, and J. Joshua Yang, “Emerging memory devices for neuromorphic computing,” Advanced Materials Technologies, vol. 4, no. 4, p. 1800589, 2019.
- Y. LeCun, Y. Bengio, and G. Hinton, “Deep learning,” Nature, vol. 521, no. 7553, pp. 436–444, 2015.
- A. Krizhevsky, I. Sutskever, and G. E. Hinton, “ImageNet classification with deep convolutional neural networks,” Advances in Neural Information Processing Systems, vol. 25, pp. 1097–1105, 2012.
- Z. Wang, H. Wu, G. W. Burr et al., “Resistive switching materials for information processing,” Nature Reviews Materials, vol. 5, no. 3, pp. 173–195, 2020.
- P. Yao, H. Wu, B. Gao et al., “Fully hardware-implemented memristor convolutional neural network,” Nature, vol. 577, no. 7792, pp. 641–646, 2020.
- F. Cai, J. M. Correll, S. H. Lee et al., “A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations,” Nature Electronics, vol. 2, no. 7, pp. 290–299, 2019.
- M. Suri, O. Bichler, D. Querlioz et al., “Phase change memory as synapse for ultra-dense neuromorphic systems: application to complex visual pattern extraction,” in 2011 International Electron Devices Meeting, Washington, DC, USA, December 2011.
- J. F. Scott and C. A. Paz de Araujo, “Ferroelectric memories,” Science, vol. 246, no. 4936, pp. 1400–1405, 1989.
- H. Toyoshima and H. Kobatake, “Features and applications of FeRAM: special issue on ferroelectric memory technology,” NEC Research & Development, vol. 40, no. 2, pp. 206–209, 1999.
- W. L. Zhong, S. T. Ai, and B. Jiang, “Two critical sizes of barium titanate and lead titanate,” Journal of Inorganic Materials, vol. 17, no. 5, pp. 1009–1012, 2002.
- N. Setter, D. Damjanovic, L. Eng et al., “Ferroelectric thin films: review of materials, properties, and applications,” Journal of Applied Physics, vol. 100, no. 5, p. 051606, 2006.
- A. I. Khan, C. W. Yeung, C. Hu, and S. Salahuddin, “Ferroelectric negative capacitance MOSFET: capacitance tuning & antiferroelectric operation,” in International Electron Devices Meeting 1998. Technical Digest (Cat. No. 98CH36217), San Francisco, CA, USA, December 1998.
- S. Kawashima, K. Morita, M. Nakazawa et al., “An 8-Mbit 0.18-μm CMOS 1T1C FeRAM in planar technology,” IEICE Transactions on Electronics, vol. 98, no. 11, pp. 1047–1057, 2015.
- T. Mikolajick, U. Schroeder, and S. Slesazeck, “The past, the present, and the future of ferroelectric memories,” IEEE Transactions on Electron Devices, vol. 67, no. 4, pp. 1434–1443, 2020.
- Y. Fang, J. Gomez, Z. Wang, S. Datta, A. I. Khan, and A. Raychowdhury, “Neuro-mimetic dynamics of a ferroelectric FET-based spiking neuron,” IEEE Electron Device Letters, vol. 40, no. 7, pp. 1213–1216, 2019.
- P. Wang and S. Yu, “Ferroelectric devices and circuits for neuro-inspired computing,” MRS Communications, vol. 10, no. 4, pp. 538–548, 2020.
- D. M. Evans, A. Schilling, A. Kumar et al., “Magnetic switching of ferroelectric domains at room temperature in multiferroic PZTFT,” Nature Communications, vol. 4, no. 1, pp. 1–7, 2013.
- T. Böscke, J. Müller, D. Bräuhaus, U. Schröder, and U. Böttger, “Ferroelectricity in hafnium oxide thin films,” Applied Physics Letters, vol. 99, no. 10, p. 102903, 2011.
- T. Francois, J. Coignus, A. Makosiej et al., “16kbit HfO2: Si-based 1T-1C FeRAM arrays demonstrating high performance operation and solder reflow compatibility,” in 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 2021.
- J. Okuno, T. Kunihiro, K. Konishi et al., “High-endurance and low-voltage operation of 1T1C FeRAM arrays for nonvolatile memory application,” in 2021 IEEE International Memory Workshop (IMW), pp. 1–3, 2021.
- T. Francois, J. Coignus, A. Makosiej et al., “High-performance operation and solder reflow compatibility in BEOL-integrated 16-kb HfO2: Si-based 1T-1C FeRAM arrays,” IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2108–2114, 2022.
- K. Tahara, K. Toprasertpong, Y. Hikosaka et al., “Strategy toward HZO BEOL-FeRAM with low-voltage operation (≤1.2 V), low process temperature, and high endurance by thickness scaling,” in 2021 Symposium on VLSI Technology, pp. 1-2, Kyoto, Japan, June 2021.
- C. Liu, Q. Wang, W. Yang et al., “Multiscale modeling of Al0.7Sc0.3N-based FeRAM: the steep switching, leakage and selector-free array,” in 2021 IEEE International Electron Devices Meeting, San Francisco, CA, USA, December 2021.
- P. C. Jamison, T. Tsunoda, T. A. Vo et al., “SiO2 free HfO2 gate dielectrics by physical vapor deposition,” IEEE Transactions on Electron Devices, vol. 62, no. 9, pp. 2878–2882, 2015.
- M. D. Glinchuk, A. N. Morozovska, and L. P. Yurchenko, “Origin of ferroelectricity and multiferroicity in binary oxide thin films,” IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 68, no. 2, pp. 273–278, 2021.
- K. W. Liu, H. H. Chen, Z. Y. Huang et al., “Investigation of phase transformation in HfO2 ferroelectric capacitor by means of a ZrO2 capping layer,” in 2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), pp. 1–3, Xi’an, China, June 2019.
- Y. C. Lin, Y. X. Huang, G. N. Huang et al., “Enhancement-mode GaN MIS-HEMTs with LaHfOx gate insulator for power application,” IEEE Electron Device Letters, vol. 38, no. 8, pp. 1101–1104, 2017.
- S. J. Kim, J. Mohan, J. Lee et al., “Effect of film thickness on the ferroelectric and dielectric properties of low-temperature (400 °C) Hf0.5Zr0.5O2 films,” Applied Physics Letters, vol. 112, no. 17, p. 172902, 2018.
- M. H. Park, Y. H. Lee, H. J. Kim et al., “Ferroelectricity and antiferroelectricity of doped thin HfO2-based films,” Advanced Materials, vol. 27, no. 11, pp. 1811–1831, 2015.
- J. Müller, P. Polakowski, S. Müller, and T. Mikolajick, “Ferroelectric hafnium oxide based materials and devices: assessment of current status and future prospects,” ECS Journal of Solid State Science and Technology, vol. 4, no. 5, pp. N30–N35, 2015.
- J. Müller, T. S. Böscke, U. Schröder et al., “Ferroelectricity in simple binary ZrO2 and HfO2,” Nano Letters, vol. 12, no. 8, pp. 4318–4323, 2012.
- J. Müller, T. S. Böscke, S. Müller et al., “Ferroelectric hafnium oxide: a CMOS-compatible and highly scalable approach to future ferroelectric memories,” in 2013 IEEE International Electron Devices Meeting, Washington, DC, USA, December 2013.
- Y. Peng, Y. Liu, G. Han, J. Zhang, and Y. Hao, “Germanium negative capacitance field effect transistors: impacts of Zr composition in Hf1-xZrxO2,” Nanoscale Research Letters, vol. 14, no. 1, p. 125, 2019.
- M. H. Park, Y. H. Lee, H. J. Kim et al., “Surface and grain boundary energy as the key enabler of ferroelectricity in nanoscale hafnia-zirconia: a comparison of model and experiment,” Nanoscale, vol. 9, no. 28, pp. 9973–9986, 2017.
- M. Pešić, U. Schroeder, S. Slesazeck, and T. Mikolajick, “Comparative study of reliability of ferroelectric and anti-ferroelectric memories,” IEEE Transactions on Device and Materials Reliability, vol. 18, no. 2, pp. 154–162, 2018.
- M. Pesic, S. Knebel, M. Hoffmann, C. Richter, T. Mikolajick, and U. Schroeder, “How to make DRAM non-volatile? Anti-ferroelectrics: a new paradigm for universal memories,” in 2016 IEEE International Electron Devices Meeting (IEDM), vol. 11, no. 16, pp. 11–14, San Francisco, CA, USA, 2016.
- S. Reyes-Lillo, K. F. Garrity, and K. M. Rabe, “Antiferroelectricity in thin-film ZrO2 from first principles,” Physical Review B, vol. 90, no. 14, p. 140103, 2014.
- R. Materlik, C. Künneth, and A. Kersch, “The origin of ferroelectricity in Hf1-xZrxO2: a computational investigation and a surface energy model,” Journal of Applied Physics, vol. 117, no. 13, p. 134109, 2015.
- M. Trentzsch, S. Flachowsky, R. Richter et al., “A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs,” in 2016 IEEE International Electron Devices Meeting (IEDM), pp. 294–297, San Francisco, CA, USA, December 2016.
- Q. Luo, T. Gong, Y. Cheng et al., “Hybrid 1T e-DRAM and e-NVM realized in one 10 nm node ferro FinFET device with charge trapping and domain switching effects,” in 2018 IEEE International Electron Devices Meeting (IEDM), vol. 2, no. 6, pp. 1–4, San Francisco, CA, USA, December 2018.
- H. Chen, X. Zhou, L. Tang et al., “HfO2-based ferroelectrics: from enhancing performance, material design, to applications,” Applied Physics Reviews, vol. 9, no. 1, p. 011307, 2022.
- Y. Xu, Y. Yang, S. Zhao et al., “Robust breakdown reliability and improved endurance in Hf0.5Zr0.5O2 ferroelectric using grain boundary interruption,” IEEE Transactions on Electron Devices, vol. 69, no. 1, pp. 430–433, 2022.
- A. Kumar, P. B. Pillai, X. Song, and M. M. De Souza, “Negative capacitance beyond ferroelectric switches,” ACS Applied Materials & Interfaces, vol. 10, no. 23, pp. 19812–19819, 2018.
- P. Sharma, Z. Huang, M. Li et al., “Oxygen stoichiometry effect on polar properties of LaAlO3/SrTiO3,” Advanced Functional Materials, vol. 28, no. 23, p. 1707159, 2018.
- A. Daus, P. Lenarczyk, L. Petti et al., “Ferroelectric-like charge trapping thin-film transistors and their evaluation as memories and synaptic devices,” Advanced Electronic Materials, vol. 3, no. 12, p. 1700309, 2017.
- H. Liu, C. Wang, G. Han et al., “ZrO2 ferroelectric FET for non-volatile memory application,” IEEE Electron Device Letters, vol. 40, no. 9, pp. 1419–1422, 2019.
- Y. Peng, W. Xiao, G. Han et al., “Memory behavior of an Al2O3 Gate dielectric non-volatile field-effect transistor,” IEEE Electron Device Letters, vol. 41, no. 9, pp. 1340–1343, 2020.
- Y. Peng, W. Xiao, F. Liu et al., “Non-volatile field-effect transistors enabled by oxygen vacancy-related dipoles for memory and synapse applications,” IEEE Transactions on Electron Devices, vol. 67, no. 9, pp. 3632–3636, 2020.
- Y. Peng, W. Xiao, G. Zhang, Y. Liu, and Y. Hao, “Synaptic behaviors in ferroelectric-like field-effect transistors with ultrathin amorphous HfO2 film,” Nanoscale Research Letters, vol. 17, no. 1, pp. 1–6, 2022.
- K. Endo, K. Kato, M. Takenaka, and S. Takagi, “Electrical characteristic of atomic layer deposition La2O3/Si MOSFETs with ferroelectric-type hysteresis,” Japanese Journal of Applied Physics, vol. 58, p. SBBA05, 2019.
- Y. Kim, A. N. Morozovska, A. Kumar et al., “Ionically-mediated electromechanical hysteresis in transition metal oxides,” ACS Nano, vol. 6, no. 8, pp. 7026–7033, 2012.
- Z. Feng, Y. Peng, Y. Shen et al., “Ferroelectric-like behavior in TaN/High-k/Si system based on amorphous oxide,” Advanced Electronic Materials, vol. 7, no. 10, p. 2100414, 2021.
- S. Mathews, R. Ramesh, T. Venkatesan, and J. Benedetto, “Ferroelectric field effect transistor based on epitaxial perovskite heterostructures,” Science, vol. 276, no. 5310, pp. 238–240, 1997.
- S.-H. Baek and C.-B. Eom, “Epitaxial integration of perovskite-based multifunctional oxides on silicon,” Acta Materialia, vol. 61, no. 8, pp. 2734–2750, 2013.
- Y. Liu, Y. Huang, and X. Duan, “van der Waals integration before and beyond two-dimensional materials,” Nature, vol. 567, no. 7748, pp. 323–333, 2019.
- D. Akinwande, C. Huyghebaert, C. H. Wang et al., “Graphene and two-dimensional materials for silicon technology,” Nature, vol. 573, no. 7775, pp. 507–518, 2019.
- K. Zhu, C. Wen, A. A. Aljarb et al., “The development of integrated circuits based on two-dimensional materials,” Nature Electronics, vol. 4, no. 11, pp. 775–785, 2021.
- M. Chhowalla, D. J. Jena, and H. Zhang, “Two-dimensional semiconductors for transistors,” Nature Reviews Materials, vol. 1, no. 11, pp. 1–15, 2016.
- Z. D. Luo, M. M. Yang, Y. Liu, and M. Alexe, “Emerging opportunities for 2D semiconductor/ferroelectric transistor-structure devices,” Advanced Materials, vol. 33, no. 12, p. 2005620, 2021.
- H. S. Lee, S. W. Min, M. K. Park et al., “MoS2 nanosheets for top-gate nonvolatile memory transistor channel,” Small, vol. 8, no. 20, pp. 3111–3115, 2012.
- C. Ko, Y. Lee, Y. Chen et al., “Ferroelectrically gated atomically thin transition-metal dichalcogenides as nonvolatile memory,” Advanced Materials, vol. 28, no. 15, pp. 2923–2930, 2016.
- X. Wang, C. Zhu, Y. Deng et al., “van der Waals engineering of ferroelectric heterostructures for long-retention memory,” Nature Communications, vol. 12, no. 1, pp. 1–8, 2021.
- L. Chen, L. Wang, Y. Peng et al., “A van der Waals synaptic transistor based on ferroelectric Hf0.5Zr0.5O2 and 2D tungsten disulfide,” Advanced Electronic Materials, vol. 6, no. 6, p. 2000057, 2020.
- Z. D. Luo, X. Xia, M. M. Yang, N. R. Wilson, A. Gruverman, and M. Alexe, “Artificial optoelectronic synapses based on ferroelectric field-effect enabled 2D transition metal dichalcogenide memristive transistors,” ACS Nano, vol. 14, no. 1, pp. 746–754, 2020.
- Z. D. Luo, S. Zhang, Y. Liu et al., “Dual-ferroelectric-coupling-engineered two-dimensional transistors for multifunctional in-memory computing,” ACS Nano, vol. 16, no. 2, pp. 3362–3372, 2022.
- M. Si, C. J. Su, C. Jiang et al., “Steep-slope hysteresis-free negative capacitance MoS2 transistors,” Nature Nanotechnology, vol. 13, no. 1, pp. 24–28, 2018.
- X. Wang, P. Yu, Z. Lei et al., “van der Waals negative capacitance transistors,” Nature Communications, vol. 10, no. 1, pp. 1–8, 2019.
- G. Wu, X. Wang, Y. Chen et al., “MoTe2 p-n homojunctions defined by ferroelectric polarization,” Advanced Materials, vol. 32, no. 16, p. 1907937, 2020.
- L. Lv, F. Zhuge, F. Xie et al., “Reconfigurable two-dimensional optoelectronic devices enabled by local ferroelectric polarization,” Nature Communications, vol. 10, no. 1, pp. 1–10, 2019.
- D. Li, M. Chen, Z. Sun et al., “Two-dimensional non-volatile programmable p-n junctions,” Nature Nanotechnology, vol. 12, no. 9, pp. 901–906, 2017.
- P. Agnihotri, P. Dhakras, and J. U. Lee, “Bipolar junction transistors in two-dimensional WSe2 with large current and photocurrent gains,” Nano Letters, vol. 16, no. 7, pp. 4355–4360, 2016.
- L. Mennel, J. Symonowicz, S. Wachter, D. K. Polyushkin, A. J. Molina-Mendoza, and T. Mueller, “Ultrafast machine vision with 2D material neural network image sensors,” Nature, vol. 579, no. 7797, pp. 62–66, 2020.
- J. W. Chen, S. T. Lo, S. C. Ho et al., “A gate-free monolayer WSe2 pn diode,” Nature Communications, vol. 9, no. 1, pp. 1–7, 2018.
- A. Lipatov, T. Li, N. S. Vorobeva, A. Sinitskii, and A. Gruverman, “Nanodomain engineering for programmable ferroelectric devices,” Nano Letters, vol. 19, no. 5, pp. 3194–3198, 2019.
- M. Bohr, “The evolution of scaling from the homogeneous era to the heterogeneous era,” in 2011 international electron devices meeting, Washington, DC, USA, December 2011.
- I R Committee et al., “International Roadmap for Devices and Systems,” 2020 edition, https://irds.ieee.org/.
- M. Si, C. Jiang, W. Chung, Y. du, M. A. Alam, and P. D. Ye, “Steep-slope WSe2 negative capacitance field-effect transistor,” Nano Letters, vol. 18, no. 6, pp. 3682–3687, 2018.
- J. Zhou, G. Han, J. Li et al., “Negative differential resistance in negative capacitance FETs,” IEEE Electron Device Letters, vol. 39, no. 4, pp. 622–625, 2018.
- J. Li, J. Zhou, G. Han et al., “Correlation of gate capacitance with drive current and transconductance in negative capacitance Ge PFETs,” IEEE Electron Device Letters, vol. 38, no. 10, pp. 1500–1503, 2017.
- Y. Liang, Z. Zhu, X. Li, S. K. Gupta, S. Datta, and V. Narayanan, “Mismatch of ferroelectric film on negative capacitance FETs performance,” IEEE Transactions on Electron Devices, vol. 67, no. 3, pp. 1297–1304, 2020.
- Y. Liang, Z. Zhu, X. Li, S. K. Gupta, S. Datta, and V. Narayanan, “Utilization of negative-capacitance FETs to boost analog circuit performances,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 12, pp. 2855–2860, 2019.
- Y. Zhao, Z. Liang, Q. Huang et al., “A novel negative capacitance tunnel FET with improved subthreshold swing and nearly non-hysteresis through hybrid modulation,” IEEE Electron Device Letters, vol. 40, no. 6, pp. 989–992, 2019.
- Z. Yu, H. Wang, W. Li et al., “Negative capacitance 2D MoS2 transistors with sub-60mV/dec subthreshold swing over 6 orders, 250 μA/μm current density, and nearly-hysteresis-free,” in 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 2017.
- J. Wang, X. Guo, Z. Yu et al., “Steep slope p-type 2D WSe2 field-effect transistors with van der Waals contact and negative capacitance,” in 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 2018.
- Z. Krivokapic, U. Rana, R. Galatage et al., “14nm ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications,” in 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 2017.
- A. K. Yadav, K. X. Nguyen, Z. Hong et al., “Spatially resolved steady-state negative capacitance,” Nature, vol. 565, no. 7740, pp. 468–471, 2019.
- M. Hoffmann, F. P. G. Fengler, M. Herzig et al., “Unveiling the double-well energy landscape in a ferroelectric layer,” Nature, vol. 565, no. 7740, pp. 464–467, 2019.
- H. Zhou, D. Kwon, A. B. Sachid et al., “Negative capacitance, n-channel, Si FinFETs: bi-directional sub-60 mV/dec, negative DIBL, negative differential resistance and improved short channel effect,” in 2018 IEEE Symposium on VLSI Technology, pp. 53-54, Honolulu, HI, USA, June 2018.
- S. Salahuddin and S. Datta, “Use of negative capacitance to provide voltage amplification for low power nanoscale devices,” Nano Letters, vol. 8, no. 2, pp. 405–410, 2008.
- Y. Peng, W. Xiao, Y. Liu et al., “HfO2-ZrO2 superlattice ferroelectric capacitor with improved endurance performance and higher fatigue recovery capability,” IEEE Electron Device Letters, vol. 43, no. 2, pp. 216–219, 2022.
- Y. Peng, G. Zhang, W. Xiao et al., “Ferroelectric-like non-volatile FET with amorphous gate insulator for supervised learning applications,” IEEE Journal of the Electron Devices Society, vol. 9, pp. 1145–1150, 2021.
- S. Zheng, J. Zhou, H. Agarwal et al., “Proposal of ferroelectric based electrostatic doping for nanoscale devices,” IEEE Electron Device Letters, vol. 42, no. 4, pp. 605–608, 2021.
- J. Zhou, G. Han, Q. Li et al., “Ferroelectric HfZrOx Ge and GeSn pMOSFETs with sub-60 mV/decade subthreshold swing, negligible hysteresis, and improved IDS,” in 2016 IEEE International Electron Devices Meeting (IEDM), pp. 395–398, San Francisco, CA, USA, December 2016.
- J. Zhou, G. Han, J. Li et al., “Comparative study of negative capacitance Ge pFETs with HfZrOx partially and fully covering gate region,” IEEE Transactions on Electron Devices, vol. 64, no. 12, pp. 4838–4843, 2017.
- A. Rusu, G. A. Salvatore, D. Jiménez, and A. M. Lonescu, “Metal-ferroelectric-meta-oxide-semiconductor field effect transistor with sub-60mV/decade subthreshold swing and internal voltage amplification,” in 2020 IEEE International Electron Devices Meeting, San Francisco, CA, USA, December 2010.
- G. Pahwa, T. Dutta, A. Agarwal et al., “Analysis and compact modeling of negative capacitance transistor with high ON-current and negative output differential resistance-part I: model description,” IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 4981–4985, 2016.
- G. Pahwa, T. Dutta, A. Agarwal et al., “Analysis and compact modeling of negative capacitance transistor with high ON-current and negative output differential resistance-part II: model validation,” IEEE Transactions on Electron Devices, vol. 63, no. 12, pp. 4986–4992, 2016.
- J. Zhou, Y. Zhou, Y. Hao et al., “Hysteresis reduction in negative capacitance Ge PFETs enabled by modulating ferroelectric properties in HfZrOx,” IEEE Journal of the Electron Devices Society, vol. 6, pp. 41–48, 2018.
- J. Zhou, J. Wu, G. Han et al., “Frequency dependence of performance in Ge negative capacitance PFETs achieving sub-30 mV/decade swing and 110 mV hysteresis at MHz,” in 2017 IEEE International Electron Devices Meeting (IEDM), pp. 373–376, San Francisco, CA, USA, December 2017.
- J. Zhou, G. Han, Y. Peng et al., “Ferroelectric negative capacitance GeSn PFETs with sub-20 mV/decade subthreshold swing,” IEEE Electron Device Letters, vol. 38, no. 8, pp. 1157–1160, 2017.
- J. Li, J. Zhou, G. Han et al., “Negative capacitance Ge PFETs for performance improvement: impact of thickness of HfZrOx,” IEEE Transactions on Electron Devices, vol. 65, no. 3, pp. 1217–1222, 2018.
- G. Han, J. Zhou, Y. Liu, J. Li, Y. Peng, and Y. Hao, “Experimental investigation of fundamentals of negative capacitance FETs,” in 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp. 1-2, Burlingame, CA, USA, October 2018.
- P. Zubko, J. C. Wojdeł, M. Hadjimichael et al., “Negative capacitance in multidomain ferroelectric superlattices,” Nature, vol. 534, no. 7608, pp. 524–528, 2016.
- B. Obradovic, T. Rakshit, R. Hatcher, J. Kittl, and M. Rodder, “Ferroelectric switching delay as cause of negative capacitance and the implications to NCFETs,” in 2018 IEEE Symposium on VLSI Technology, pp. 51-52, Honolulu, HI, USA, June 2018.
- J. Zhou, G. Han, N. Xu et al., “Incomplete dipoles flipping produced near hysteresis-free negative capacitance transistors,” IEEE Electron Device Letters, vol. 40, no. 2, pp. 329–332, 2019.
- J. Zhou, G. Han, N. Xu et al., “Experimental validation of depolarization field produced voltage gains in negative capacitance field-effect transistors,” IEEE Transactions on Electron Devices, vol. 66, no. 10, pp. 4419–4424, 2019.
- Y. Peng, W. Xiao, G. Han et al., “Nanocrystal-embedded-insulator ferroelectric negative capacitance FETs with sub-kT/q swing,” IEEE Electron Device Letters, vol. 40, no. 1, pp. 9–12, 2018.
- T. Gong, L. Tao, J. Li et al., “105× endurance improvement of FE-HZO by an innovative rejuvenation method for 1z node NV-DRAM applications,” in 2021 Symposium on VLSI Technology, pp. 1-2, Kyoto, Japan, June 2021.
- D. R. Islamov, T. M. Zalyalov, O. M. Orlov, V. A. Gritsenko, and G. Y. Krasnikov, “Impact of oxygen vacancy on the ferroelectric properties of lanthanum-doped hafnium oxide,” Applied Physics Letters, vol. 117, no. 16, p. 162901, 2020.
- S. C. Chang, N. Haratipour, S. Shivaraman et al., “FeRAM using anti-ferroelectric capacitors for high-speed and high-density embedded memory,” in 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 2021.
- Y.-C. Luo, J. Hur, Z. Wang, W. Shim, A. I. Khan, and S. Yu, “A technology path for scaling embedded FeRAM to 28 nm and beyond with 2T1C structure,” IEEE Transactions on Electron Devices, vol. 69, no. 1, pp. 109–114, 2022.
- J. Okuno, T. Kunihiro, K. Konishi et al., “SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2,” in 2020 IEEE Symposium on VLSI Technology, Honolulu, HI, USA, June 2020.
- T. Mittmann, M. Materano, S.-C. Chang, I. Karpov, T. Mikolajick, and U. Schroeder, “Impact of oxygen vacancy content in ferroelectric HZO films on the device performance,” in 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 2020.
- T. Onaya, T. Nabatame, N. Sawamoto et al., “Improvement in ferroelectricity of HfxZr1−xO2 thin films using ZrO2 seed layer,” Applied Physics Express, vol. 10, no. 8, p. 081501, 2017.
- Y. Lee, Y. Goh, J. Hwang, D. Das, and S. Jeon, “The influence of top and bottom metal electrodes on ferroelectricity of hafnia,” IEEE Transactions on Electron Devices, vol. 68, no. 2, pp. 523–528, 2021.
- W. Xiao, P. Peng, Y. Liu et al., “Hf0.5Zr0.5O2 1T-1C FeRAM arrays with excellent endurance performance for embedded memory,” Tech. Rep., Science China Information Sciences, 2022.
- S. Dünkel, M. Trentzsch, R. Richter et al., “A FeFET based super-low-power ultra-fast embedded NVM technology for 22nm FDSOI and beyond,” in 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 2017.
- H. Mulaosmanovic, E. T. Breyer, S. Dünkel, S. Beyer, T. Mikolajick, and S. Slesazeck, “Ferroelectric field-effect transistors based on HfO2: a review,” Nanotechnology, vol. 32, no. 50, p. 502002, 2021.
- Y. Peng, G. Han, F. Liu et al., “Ferroelectric-like behavior originating from oxygen vacancy dipoles in amorphous film for non-volatile memory,” Nanoscale Research Letters, vol. 15, no. 1, p. 134, 2020.
- G. Zhang, Y. Peng, W. Xiao et al., “Synaptic plasticity in novel non-volatile FET with amorphous gate insulator enabled by oxygen vacancy related dipoles,” in 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), pp. 1–3, Chengdu, China, April 2021.
- H. Liu, Y. Peng, G. Han et al., “ZrO2 ferroelectric field-effect transistors enabled by the switchable oxygen vacancy dipoles,” Nanoscale Research Letters, vol. 15, no. 1, p. 120, 2020.
- H. Liu, J. Li, G. Wang et al., “Analog synapses based on nonvolatile FETs with amorphous ZrO2 dielectric for spiking neural network applications,” IEEE Transactions on Electron Devices, vol. 69, no. 3, pp. 1028–1033, 2022.
- Z. Wang, B. Crafton, J. Gomez et al., “Experimental demonstration of ferroelectric spiking neurons for unsupervised clustering,” in 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 2018.
- C. Chen, M. Yang, S. Liu et al., “Bio-inspired neurons based on novel leaky-FeFET with ultra-low hardware cost and advanced functionality for all-ferroelectric neural network,” in 2019 Symposium on VLSI Technology, pp. T136–T137, Kyoto, Japan, June 2019.
- J. Luo, L. Yu, T. Liu et al., “Capacitor-less stochastic leaky-FeFET neuron of both excitatory and inhibitory connections for SNN with reduced hardware cost,” in 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 2019.
- Y. Peng, N. Xu, T. J. K. Liu et al., “Nanocrystal-embedded-insulator (NEI) ferroelectric field-effect transistor featuring low operating voltages and improved synaptic behavior,” IEEE Electron Device Letters, vol. 40, no. 12, pp. 1933–1936, 2019.
- M. Jerry, P. Y. Chen, J. Zhang et al., “Ferroelectric FET analog synapse for acceleration of deep neural network training,” in 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, December 2017.
- M.-C. Nguyen, K. Lee, S. Kim et al., “Incremental drain-voltage-ramping training method for ferroelectric field-effect transistor synaptic devices,” IEEE Electron Device Letters, vol. 43, no. 1, pp. 17–20, 2022.
- K.-Y. Hsiang, C. Y. Liao, K. T. Chen et al., “Ferroelectric HfZrO2 with electrode engineering and stimulation schemes as symmetric analog synaptic weight element for deep neural network training,” IEEE Transactions on Electron Devices, vol. 67, no. 10, pp. 4201–4207, 2020.
- J. Noh, H. Bae, J. Li et al., “First experimental demonstration of robust HZO/β-Ga₂O₃ ferroelectric field-effect transistors as synaptic devices for artificial intelligence applications in a high-temperature environment,” IEEE Transactions on Electron Devices, vol. 68, no. 5, pp. 2515–2521, 2021.
- K. Ni, P. Sharma, J. Zhang et al., “Critical role of interlayer in Hf0.5Zr0.5O2 ferroelectric FET nonvolatile memory performance,” IEEE Transactions on Electron Devices, vol. 65, no. 6, pp. 2461–2469, 2018.
- K. Ni, X. Li, J. A. Smith, M. Jerry, and S. Datta, “Write disturb in ferroelectric FETs and its implication for 1T-FeFET and memory arrays,” IEEE Electron Device Letters, vol. 39, no. 11, pp. 1656–1659, 2018.
- G. Choe, A. Lu, and S. Yu, “3D AND-type ferroelectric transistors for compute-in-memory and the variability analysis,” IEEE Electron Device Letters, vol. 43, no. 2, pp. 304–307, 2022.
- A. Chouprik, A. Chernikova, A. Markeev et al., “Electron transport across ultrathin ferroelectric Hf0.5Zr0.5O2 films on Si,” Microelectronic Engineering, vol. 178, pp. 250–253, 2017.
- A. Gruverman, D. Wu, H. Lu et al., “Tunneling electroresistance effect in ferroelectric tunnel junctions at the nanoscale,” Nano Letters, vol. 9, no. 10, pp. 3539–3543, 2009.
- V. Garcia, S. Fusil, K. Bouzehouane et al., “Giant tunnel electroresistance for non-destructive readout of ferroelectric states,” Nature, vol. 460, no. 7251, pp. 81–84, 2009.
- F. Liu, L. You, K. L. Seyler et al., “Room-temperature ferroelectricity in CuInP2S6 ultrathin flakes,” Nature Communications, vol. 7, no. 1, p. 12357, 2016.
- S. Wan, Y. Li, W. Li et al., “Nonvolatile ferroelectric memory effect in ultrathin α-In2Se3,” Advanced Functional Materials, vol. 29, no. 20, p. 1808606, 2019.
- W. Wu, H. Wu, B. Gao, N. Deng, S. Yu, and H. Qian, “Improving analog switching in HfOx-based resistive memory with a thermal enhanced layer,” IEEE Electron Device Letters, vol. 38, no. 8, pp. 1019–1022, 2017.
- L. Chen, T. Y. Wang, Y. W. Dai et al., “Ultra-low power Hf0.5Zr0.5O2 based ferroelectric tunnel junction synapses for hardware neural network applications,” Nanoscale, vol. 10, no. 33, pp. 15826–15833, 2018.
- S. Fujii, Y. Kamimuta, T. Ino, Y. Nakasaki, R. Takaishi, and M. Saitoh, “First demonstration and performance improvement of ferroelectric HfO2 resistive switch with low operation current and intrinsic diode property,” in 2016 IEEE Symposium on VLSI Technology, pp. 1-2, Honolulu, HI, USA, June 2016.
- Y. Goh, J. Hwang, M. Kim et al., “High performance and self-rectifying hafnia-based ferroelectric tunnel junction for neuromorphic computing and TCAM applications,” in 2021 IEEE International Electron Devices Meeting (IEDM), pp. 378–381, San Francisco, CA, USA, December 2021.
- H. Ryu, H. Wu, F. Rao, and W. Zhu, “Ferroelectric tunneling junctions based on aluminum oxide/zirconium-doped hafnium oxide for neuromorphic computing,” Scientific Reports, vol. 9, no. 1, pp. 1–8, 2019.
- Y. Xiao, S. Deng, Z. Zhao, V. Narayanan, and K. Ni, “Predictive modeling of ferroelectric tunnel junctions for memory and analog weight cell applications,” in 2021 IEEE International Electron Devices Meeting, pp. 342–345, San Francisco, CA, USA, December 2021.
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