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Hello Marchzh,

Please find attached the test results for input power (BB gain and 3dB att refers to TRF3711 settings). Best Regards,

Peter

Please find attached the test results for input power (BB gain and 3dB att refers to TRF3711 settings). Best Regards,

Peter

[quote author=arnaudNL link=topic=2357.msg12130#msg12130 date=1381476258]

Dear Sir,

1)

There are 14 bits of data which are left aligned on 16 bits word.

The data is placed on bits 13 down to 2, bits 1 and 0 being nothing. I Q interleaved means that the sequence in the buffer looks like the following

I0Q0I1Q1I2Q2I3Q3...

2)

I will get one of my colleague to provide you with this information, it is not part of the user manual indeed.

[/quote]

Dear Sir,

I am also eager to know [size=78%] a) What is acceptable input range of RF IN for dBM and voltages?[/size] b) What is a good nominal value? Can you invite your colleague to answer this. I would be very grateful.

Thanks.

Marchzh

Dear Sir,

1)

There are 14 bits of data which are left aligned on 16 bits word.

The data is placed on bits 13 down to 2, bits 1 and 0 being nothing. I Q interleaved means that the sequence in the buffer looks like the following

I0Q0I1Q1I2Q2I3Q3...

2)

I will get one of my colleague to provide you with this information, it is not part of the user manual indeed.

[/quote]

Dear Sir,

I am also eager to know [size=78%] a) What is acceptable input range of RF IN for dBM and voltages?[/size] b) What is a good nominal value? Can you invite your colleague to answer this. I would be very grateful.

Thanks.

Marchzh

Dear Sir,

From the VHDL source code delivered with the BSP:

rx_data_i <= adc_i & "0000";

dac_a <= tx_data_i(15 downto 4);

Best Regards,

Arnaud

From the VHDL source code delivered with the BSP:

rx_data_i <= adc_i & "0000";

dac_a <= tx_data_i(15 downto 4);

Best Regards,

Arnaud

Just to make sure I really understand 14 bit 16 bit left aligned:

Take 14 bit vector and concatenate two zeroes into bit 0 and bit 1 to make a 16 bit vector

VHDL

(14 bit vector) & '0' & '0'

Take 14 bit vector and concatenate two zeroes into bit 0 and bit 1 to make a 16 bit vector

VHDL

(14 bit vector) & '0' & '0'

Dear Sir,

1)

There are 14 bits of data which are left aligned on 16 bits word.

The data is placed on bits 13 down to 2, bits 1 and 0 being nothing. I Q interleaved means that the sequence in the buffer looks like the following

I0Q0I1Q1I2Q2I3Q3...

2)

I will get one of my colleague to provide you with this information, it is not part of the user manual indeed.

1)

There are 14 bits of data which are left aligned on 16 bits word.

The data is placed on bits 13 down to 2, bits 1 and 0 being nothing. I Q interleaved means that the sequence in the buffer looks like the following

I0Q0I1Q1I2Q2I3Q3...

2)

I will get one of my colleague to provide you with this information, it is not part of the user manual indeed.

## Customer

1) Please elaborate what 14 bit 16 bit left aligned complex samples mean.

In Reference Design Details at the end there is a statement:

- The data format is 14-bit, 16-bit left aligned complex samples with I and Q samples interleaved.

2) I want to inject a signal into RF IN of FMC30RF from a agilent analog generator.

a) A sine wave offset from tx tune frequency.

b) What is acceptable input range of RF IN for dBM and voltages?

c) What is a good nominal value?